1. Field of the Invention
The present invention relates to a method for reading a NAND flash memory device and a memory cell array thereof, and more particularly, to a method for reading a NAND flash memory device, which stores two-bit information per memory cell and a memory cell array thereof.
2. Description of the Related Art
In a traditional NAND flash memory device, memory cells can take one of two information storing states, namely, the “ON” state and “OFF” state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a positive integer of 2 or greater) in the aforesaid traditional NAND flash memory device, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a NAND flash memory device having one-bit memory cells, the number of such memory cells should increase accordingly. Information stored in the one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell to switch the cell transistor to its ON state.
FIG. 1 shows a threshold voltage distribution of a memory cell according to programmed data. As shown in FIG. 1, a programmed data exhibits one of a threshold voltage (indicating 2-bit data of (11)) lower than −2.0V, a threshold voltage (indicating 2-bit data of (10)) between 0.7V to 1.1V, a threshold voltage (indicating 2-bit data of (01)) between 2.0V to 2.4V, and a threshold voltage (indicating 2-bit data of (00)) between 3.6V to 4.0V. Data can be stored in four different stages in one memory cell on the basis of such threshold voltage distributions.
As for the read operation applied to single level memory cells, U.S. Pat. No. 6,671,204 (hereinafter '204) proposes a method to read the data stored in a memory cell. FIG. 2(a) shows a page buffer of '204, which describes the data flow during the read operation and FIG. 2(b) is a timing chart of the signal commands regarding FIG. 2(a). The detailed read operation is given below. Data is assumed to be read out from one of the memory cells (not shown) and gate control signals of the memory cells to be read apply appropriate voltages to word lines. Reading out is performed directly through a main register 150, bypassing an auxiliary register 170. In order to perform a stable read operation, two bit lines BLE and BLO are first discharged through the transistors N1 and N2 by zeroing a signal VIRPWR, and activating the control signals VBLe and VBLo (refer to Region 1 of FIG. 2(b)). At the same time, a signal PBRST activates from a high logic state to a low logic state to turn on a transistor N5, so that a state of the main register 150 (or an input of an inverter 153) is set to a predetermined state (i.e., a logic high state). Afterwards, entering Region 2, a first control signal PLOAD goes low and the transistor N9 is turned on. The control signal BLSHFe of the transistor N3 is made to have a voltage (e.g., 2.1V) of summing the bit line precharge voltage and a threshold voltage of the transistor N3. After precharging the bit line BLE with an appropriate voltage, the control signal BLSHFe goes to a logic low state of the ground voltage (refer to Region 3). In Region 3, a precharged voltage of the bit line varies according to a state of a selected memory cell. For example, in the case where the selected memory cell is an off cell (i.e., the word line voltage applied is lower than the threshold voltage of the selected memory cell), the precharged voltage of the bit line continues to be maintained. In the case where the selected memory cell is an on cell (i.e., the word line voltage applied is higher than the threshold voltage of the selected memory cell), the precharged voltage of the bit line is discharged. If a voltage of the control signal BLSHFe is changed into an intermediate voltage between the precharge voltage and the previous BLSHFe signal level, a voltage of a node SO is maintained at the source voltage (Vcc) by shutting off the transistor N3 when the selected memory cell is an off cell. If not, however, a voltage of the node SO is discharged along the bit line BLE voltage. At a midway point where the control signal BLSHFe goes to a logic low state of the ground voltage, the first control signal PLOAD turns to a high logic state. After that, entering Region 4, the signal PBLCHM goes to a high logic state to turn on the transistor N7, and the transistor N6 is turned on or off according to the state of the node SO. As a result, the state of the node SO is stored in the main register 150. Then, the data stored in the main register 150 is transferred to a data line 131 via the transistor N8, which is controlled by the signal PBDO, and next via a Y-gating circuit 130 (Region 6).
As for the read operation applied to a multi-level memory cell, U.S. Pat. No. 5,754,475 (hereinafter '475) proposes a multi-level-cell reading method. FIG. 3 is a simplified block diagram of a read circuit of '475 associated with the memory cells of one block. The memory cells MC11 through MCnm of the array 112 are arranged in the form of a matrix. The memory cells MC11, MC12, . . . MC1m are arranged in the same row and have their selection terminals connected to the same common word line WL1. This is likewise done for each of the remaining rows in the array 112. Also, the memory cells MC11, MC21 . . . MCnl; the memory cells MC12, MC22 . . . MCn2; . . . and the memory cells MC1m, MC2m, . . . MCnm are arranged in the same respective columns and have their corresponding data terminals connected to associated common bit lines BL1, BL2 . . . BLn, respectively. Three reference bit lines 122a through 122c per page are used for four-level cells. Each reference bit line 122 has a reference cell RC at the intersection with each word line WL. The threshold voltage of the reference cells RC on a page are tuned to the targeted value while the page program is instructed, and the reference cells RC are programmed with the normal cells MC concurrently. The reference cells have the threshold voltages RT0, RT1 and RT2 as shown in FIG. 1. To distinguish the four levels (i.e., four states of (11), (10), (01) and (00)) in a memory cell, the read operation needs to repeat three times (i.e., three phases) and each read operation is performed as shown in FIG. 2(b). In Phase 1, the MSB (most significant bit) of the two-bit data stored in the memory cells with the states of (11), (10), (01) and (00) is read. In Phase 2, the LSB (least significant bit) of the two-bit data stored in the memory cells with the states of (11) and (10) is read. In Phase 3, the LSB of the two-bit data stored in the memory cells with the states of (01) and (00) is read. The reading sequence of the read operation of '475 is shown in FIG. 4(a).
In U.S. Pat. No. 5,768,188 (hereinafter '188), a read method regarding a multi-level-cell NAND memory device is disclosed. The read method employs three phases with different constant word line voltages to distinguish one of the four states stored in a memory cell without reference cells. The LSB of the two-bit data stored in the memory cells with the states of (01) and (00) is detected in Phase 1 with the selected word line voltage of 2V; then, the MSB of the two-bit data stored in the memory cells with the states of (11), (10), (01) and (00) is detected in Phase 2 with the selected word line voltage of 1V; finally, the LSB of the two-bit data stored in the memory cells with the states of (11) and (10) is read in Phase 3 with the selected word line voltage of 0V. The reading sequence of the read operation of '188 is shown in FIG. 4(b).
In U.S. Pat. No. 2005/0018488 (hereinafter '488), a read method regarding a multi-level-cell NAND memory device is disclosed. The read method also employs three phases with different constant word line voltages to distinguish one of the four states stored in a memory cell without reference cells. The read sequence is different from those of '475 and '188. The LSB of the two-bit data stored in the memory cells with the states of (01) and (00), the LSB of the two-bit data stored in the memory cells with the states of (11) and (10) and the MSB of the two-bit data stored in the memory cells with the states of (11), (10), (01) and (00) are read in Phases 1, 2 and 3, respectively. The three different selected word line voltages are 2V, 0V and 1V for Phases 1, 2 and 3, respectively. The reading sequence of the read operation of '488 is shown in FIG. 4(c).
In U.S. Pat. No. 5,986,929 (hereinafter '929), a read method regarding a multi-level-cell NAND memory device is disclosed. The read method also employs three phases with different constant word line voltages to distinguish one of the four states stored in a memory cell without reference cells. The read sequence is different from those of '475, '188 and '488. The LSB of the two-bit data stored in the memory cells with the states of (11) and (10), the MSB of the two-bit data stored in the memory cells with the states of (11), (10), (01) and (00) and the LSB of the two-bit data stored in the memory cells with the states of ((01) and (00) are read in Phases 1, 2 and 3, respectively. The three different selected word line voltages are 0V, 1.2V and 2.4V for Phases 1, 2 and 3, respectively. The reading sequence of the read operation of '929 is shown in FIG. 4(d).